Telephone answering machines employing tape recorders for recording incoming messages are now commonly available. A first problem exists in that each of these machines employs a costly tape transport mechanism which must be assembled and adjusted during manufacturing, and which is subject to mechanical wear. A second problem exists in that each of these machines includes at least one head for erasing data from the tape, writing new data to the tape, and reading data from the tape, and also includes corresponding electronic circuitry for providing proper signals to the record head, and for receiving, amplifying, and demodulating signals from the read head. A third problem exists in that the tape transport mechanism is motor-driven and consumes a relatively large amount of power.
One skilled in the art might consider digitizing the incoming audio messages and storing them in a memory device. A suitable memory size for an application in an answering machine is approximately 1 Mbit (i.e., a memory chip having 1,048,576 data storage locations, each capable of holding 1 bit of data). Such a 1 Mbit dynamic random access memory integrated circuit (DRAM, or dynamic RAM) is known from the TI TMS4C102, manufactured by Texas Instruments Corporation, Dallas Tex. This DRAM is organized as a 1,048,576 X 1 array of memory locations.
However, heretofore the use of a 1 Mbit dynamic RAM was impractical, because while the computer industry commonly employs 1 Mbit DRAMs (hereinafter referred to as "computer grade" DRAM), the cost of such 1 Mbit DRAM chips is prohibitively high for consumer products. The cost is high because, as noted above, each DRAM chip has 1,048,576 memory locations, each of which must function perfectly. This constraint causes relatively low yields of good DRAM chips and relatively high yields of DRAM chips which are unusable by the computer industry.